data sheet 27463.1 preliminary ? subject to change without notice february 9, 2004 a8420/a8421 lin bus transceiver with integrated voltage regulator the a8420 and a8421 provide the physical interface requirements of the lin (local interconnect network) serial communications bus plus either a signal to control an external supply (in the a8420), or an inte- grated voltage regulator (in the a8421). these allow the development of simple, inexpensive slave nodes in a lin-bus system. the lin transceiver is compatible with lin-bus systems that conform to the lin protocol speci cation, revision 1.2. it provides all the necessary interface and timing control to convert signals to and from the bidirectional lin bus to individual transmit and receive signals at logic-compatible levels. the a8421 provides regulated 5v output with a current limit in excess of 50 ma. this is suf cient to power a microcontroller handling the lin slave node protocol. the a8420 and a8421 are supplied in 8-lead plastic soic (part number suf x l ). compatible with lin bus, revision 1.2 systems data rate up to 20 kbaud normal operation from 7 to 30 v handles 40 v transients during load dump handles automotive transients per iso 7637 unpowered node does not disturb the network 4 kv (hbm) esd protection on lin and wake pins two options: control for external supply (a8420) or regulated supply for slave microcontroller (a8421) interface to slave microcontroller 8-pin small outline surface mount package use the following complete part numbers when ordering: ab so lute max i mum rat ings part number package description A8420KL 8-lead, soic inh switch output a8421kl 8-lead, soic voltage regulator supply voltage, vsup continuous..................... 30 v supply voltage, vsup transient (500 ms)......... 40 v lin bus voltage, lin........................... ?18 to +40 v wake pin ............................................... ?18 to +40 v logic pins: rx, tx, en ...................... ?0.3 v to 7 v package power dissipation, p d ....... see chart, page 6 operating temperature range ambient temperature, t a ........... ?40c to +125c junction temperature, t j ............ ?55c to +150c storage temperature, t s .......... ?55c to +150c features a8420 soic a8421 soic 2 3 4 1 7 6 5 8 rx en wake tx vreg vsup lin gnd control regulator applications automotive, industrial, and consumer lin-bus systems 2 3 4 1 7 6 5 8 rx en wake tx inh vsup lin gnd control switch
2 worcester, massachusetts 01615-0036 (508) 853-5000 115 northeast cutoff, box 15036 www.allegromicro.com data sheet 27463.1 a8420/a8421 lin bus transceiver with integrated voltage regulator preliminary ? subject to change without notice february 9, 2004 electrical characteristics at t j = ?40c to 150oc, v sup = 7 v to 18 v (unless otherwise noted) characteristics symbol test conditions min. typ. max. units vsup power supply operating voltage range v sup continuous 7 ? 30 v transient; 500 ms ? ? 40 v supply current i sup lin output recessive (high); v wake = 0 ? 0.8 1 ma lin output dominant (low); v wake = 0 ? 1.5 2 ma supply standby current i stby v wake = 0, lin = n.c. ? 0.8 1 ma lin = dominant (low), wake = n.c. ? 1.5 2 ma supply sleep current i sleep ? 6 10 a undervoltage threshold vsup uv 4.8 5.0 5.2 v tx and en input low level input voltage v il ? ? 0.8 v high level input voltage v ih 2??v input hysteresis v ihys ? 300 ? mv pull-down resistor r pd en pin 60 100 200 k ? pull-up resistor r pu tx pin 60 100 200 k ? rx output low level output current i ol v rx = 0.4 v 1.5 ? ? ma high level leakage current i oh v rx = 5 v ? ? 5 a wake input low level input voltage v il ??v sup -5 v high level input voltage v ih v sup ?1 ? ? v pull-up current i il v wake = 0 v ? 40 ? a high level leakage current i ih v wake = v sup = 30 v ? ? 5 a inh output (a8420 only) on resistance vsup to inh r on i o = 15 ma ? 40 100 ? off leakage current i ol ??5a vreg regulated 5v supply (a8421 only) output voltage v reg i out = 0 to 50 ma 4.5 5.0 5.5 v output current limit ireg lim v reg = 0 v ? ? 180 ma external decoupling cap v reg to gnd 1 ? ? f line regulation i out = 30 ma ? ? 100 mv load regulation v sup = 13.5 v; i out = 1 to 30 ma ? ? 100 mv lin interface output short circuit current i osc 60 85 110 ma output voltage ? recessive v or v tx = 5 v; i lin = 0 ma 0.9 v sup ??v output voltage ? dominant v od v tx = 0 v; i lin = 40 ma ? 1 1.2 v high level leakage current i ih v lin = v sup ? ? 10 a termination resistance r slave 20 30 47 k ? input threshold ? dominant v thdom v lin ? recessive to dominant 0.4 v sup ??v input threshold ? recessive v threc v lin ? dominant to recessive ? ? 0.6 v sup v input threshold hysteresis vlin hys 0.05 v sup 0.1 v sup 0.175 v sup v
3 worcester, massachusetts 01615-0036 (508) 853-5000 115 northeast cutoff, box 15036 www.allegromicro.com data sheet 27463.1 a8420/a8421 lin bus transceiver with integrated voltage regulator preliminary ? subject to change without notice february 9, 2004 dynamic characteristics at t j = ?40c to 150oc, v sup = 7 v to 18 v (unless otherwise noted) characteristics symbol test conditions min. typ. max. units lin falling edge slew rate 1 s hl 80% to 20% 1 2 3 v/s lin rising edge slew rate 1 s lh 20% to 80% into >1 k ? and < 5 nf 1 2 3 v/s 20% to 80% into >1 k ? and < 10 nf ? 1 ? v/s lin rise fall symmetry t sym 20% to 80% into > 1 k ? and < 5 nf ?2 ? 2 s tx propagation delay h lt txl tx h l; lin crossing 95% ? 1.5 4 s tx propagation delay l ht txh tx l h; lin crossing 5% ? 1.5 4 s tx propagation delay matching ? ? 2 s rx propagation delay h lt rxl lin crossing 40%; rx crossing 50% ? 3 6 s rx propagation delay l ht rxh lin crossing 60%; rx crossing 50% ? 3 6 s rx propagation delay matching ? ? 2 s glitch rejection t glr +ve and -ve pulse rejection on lin (to rx) ? 1.8 ? s wake-up delay (lin or wake) t wl wake-up to inh or vreg 90% ? 50 ? s thermal shutdown shutdown temperature t sd ? 165 ? oc thermal shutdown hysteresis t hys ?20?oc 1 slew rate is controlled during both transitions and will not exceed speci ed limits at any point between test limits. 40% 60% 5% 95% 50% 50% t txl t txh t rxl t rxh tx rx lin figure 1. propagation timing de nition 80 20 lin s lh t v lin s hl (%) figure 2. slew rate de nition
4 worcester, massachusetts 01615-0036 (508) 853-5000 115 northeast cutoff, box 15036 www.allegromicro.com data sheet 27463.1 a8420/a8421 lin bus transceiver with integrated voltage regulator preliminary ? subject to change without notice february 9, 2004 power supply. the device power supply, 13.5 v nominal for automotive applications, is connected to the battery through an external diode, in order to protect against reversal of battery polarity. to comply with the lin bus protocol, there must be no more than a 1 v drop between the bat- tery potential and the supply pin. the a8420/a8421 oper- ates continuously up to 30 v, and withstands 40 v during a 500 ms load dump. if the supply drops below the undervolt- age limit, this condition is detected and the a8420/a8421 disables the transmission path, while maintaining a high- impedance state on the lin terminal. the a8420/a8421 does not disturb the lin bus in the case of ground disconnection at the module level. in addition, full functionality is maintained with a ground shift of up to 8 v, provided that the difference between gnd and vsup is greater than the undervoltage threshold. lin bus interface. the a8420/a8421 integrates all components required to drive and monitor the single-wire lin bus as a slave node. an external resistor, diode, and capacitor are normally required for the a8420/a8421 to function as a master node. the lin pin can withstand volt- ages from +40 v to ?18 v with respect to the gnd pin with- out adversly affecting lin bus communications between other devices. when the a8420/a8421 is in sleep mode or standby mode, the lin pin is in the recessive state. when the a8420/a8421 is the active interface on the lin bus, it controls the rise and fall slew rates of the voltage level on the lin pin, such that the rising or falling slew rate does not exceed the speci ed limits at any point between the 20% and 80% levels. if, while in sleep mode, the a8420/a8421 detects the lin bus transitioning into the dominant state, a wake-up signal is generated. this transitions the device from sleep mode into standby mode. the data to be transmitted is input to the tx pin and con- verted to lin bus signals. a logic high on this pin produces a recessive bus (high) state while a logic low produces a dominant bus (low) state. the tx input has an internal pull-up resistor to ensure a recessive state if the pin is not connected or becomes disconnected. the state of the lin bus is determined by the receiver and output as a logic level on the rx pin. this pin is open drain. in normal mode, rx is active (pull-down) when the lin bus is in the dominant (low) state, and rx is inactive (high-z) when the lin bus is in the recessive (high) state. functional description normal standby sleep en 1 active=t en 0 en 1 a ctive t por a ctive f uvlo active=f en 0 figure 3. operating state. active is true (t) if wake is low (l) or if lin is low (l). otherwise, active is false (f). the uvlo feature overrides. logic functions inputs state outputs tx en wake lin rx lin inh vreg 1 1 * h norm z rec(z) v sup 5v 1 1 * l norm l rec(z) v sup 5v 0 1 * * norm l dom(l) v sup 5v *0 l 1 * standby l rec(z) v sup 5v *0 * l 1 standby l rec(z) v sup 5v *0 h 1 h 1 sleep z rec(z) z z * 1 * * uvlo z rec(z) z off * 1 * h tsd z rec(z) v sup 5v * 1 * l tsd l rec(z) v sup 5v 1 sleep mode is entered only when lin is high, wake is high, and en goes to 0. the a8420/a8421 remains in standby mode when wake or lin is low. 2 z = high impedance, * = don?t care.
5 worcester, massachusetts 01615-0036 (508) 853-5000 115 northeast cutoff, box 15036 www.allegromicro.com data sheet 27463.1 a8420/a8421 lin bus transceiver with integrated voltage regulator preliminary ? subject to change without notice february 9, 2004 in sleep mode rx is not active (high-z). when in standby mode, rx asserts an active low and can be used to indicate to the controlling device that either the wake signal has gone low or that a dominant sate is present on the lin bus, indi- cating that the bus has become active. operating mode. the a8420/a8421 has three modes of operation: normal, standby, and sleep. the enable input, en, determines whether normal mode is maintained (en high) or one of the two inactive modes, standby or sleep, are entered (en low). if no other wake-up signals are active, en low sets the a8420/a8421 into low-current sleep mode. from sleep mode the a8420/a8421 can be put directly into normal mode by taking en high. alternatively, it can be taken into standby mode by pulling the wake input to ground or by a dominant state on the lin bus. in sleep mode, the supply current is at its minimum level, and the lin and rx pins are high impedance. in this mode, the inh output (a8420) or the linear regulator output (a8421) are off. when the power is rst applied, the a8420/a8421 enters sleep mode directly. from sleep mode, the a8420/a8421 may be taken through the standby mode, where the inh or linear regulator are activated, in order to provide power to the protocol con- trol device attached to the tx, rx, and en pins. once the controller is active, it may then bring the a8420/a8421 into normal mode by taking en high. if there is no need to pro- vide power prior to enabling the a8420/a8421, then simply asserting en high moves the a8420/a8421 directly from sleep mode to normal mode. the en input has an internal pull-down resistor to ensure a known safe state when the protocol controller is powered off. the wake signal is a high-voltage input, which is designed to allow a node on a sleeping bus to be awaken by a local event. sleep mode may be entered when wake is connected directly to the battery or other similar voltage, such as vsup. to disable sleep mode and allow the a8420/a8421 to enter standby mode, the wake input should be switched to ground. the a8420/a8421 incorporates two protection functions. if the die temperature becomes excessive, a thermal shutdown feature (tsd) disables the lin output dominant-state drive. once the temperature falls below the hysteresis level, the lin output resumes the state de ned by the tx input. dur- ing tsd, the output on inh or vreg is maintained. if the supply voltage drops below the uvlo threshold, all outputs are disabled. when the supply voltage rises above the uvlo threshold, the a8420/a8421 is reset into the sleep mode. from that state, it follows the logic shown in gure 1. that is, if active is true (t), the a8420/a8421 immediately goes to standby mode. if en is high, it goes directly to the normal mode. optional functions . the two options, the a8420 and the a8421, provide alternatives for powering additional circuits. the a8420 provides an inh output, a low-impedance (typically 50 ? ) connection to vsup in normal or standby mode. in sleep mode, this output is high-impedance. inh is intended to be used to control an external power supply, such that it powers-up and powers-down according to the lin bus or the local w ake si gnal. the a8421 provides a linear regulator output with speci ed line and load regulation up to 30 ma at 5 v. the regulator output is current-limited, at typically 100 ma. care must be taken, however, when operating above 30 ma, due to power dissipation. this is especially important under fault condi- tions such as load dump. as is the case with the inh option, this output is only active in standby or normal mode. this
6 worcester, massachusetts 01615-0036 (508) 853-5000 115 northeast cutoff, box 15036 www.allegromicro.com data sheet 27463.1 a8420/a8421 lin bus transceiver with integrated voltage regulator preliminary ? subject to change without notice february 9, 2004 0.0 0.2 0.4 0.6 0.8 1.0 1.2 25 50 75 100 125 150 allowable package power dissipation, p d (a8420 and a8421) ambient temperature (oc) power (w) "high k" r ja = 80oc/w fr4 r ja = 140oc/w 0.0 10.0 20.0 30.0 40.0 50.0 60.0 25 50 75 100 125 available current (a8421 only) ambient temperature (oc) current (ma) 24 v 40 v fr4 r ja = 140oc/w 7 v 12 v 18 v 0.0 10.0 20.0 30.0 40.0 50.0 60.0 25 50 75 100 125 available current (a8421 only) ambient temperature (oc) current (ma) 12 v 24 v "high k" r ja = 80oc/w 7 v 18 v 40 v output will supply suf cient current for a simple microcon- troller operating as a protocol controller. power dissipation. for the a8421, most power will normally be dissipated in the linear regulator. because the output of the regulator is xed at 5 v, but the input supply can vary between 7 v and 18 v, care must be taken when setting the maximum current. this is particularly important if the ability of the a8421 to withstand a 40 v load dump is to be used. this limitation does not apply to the a8420, which has a simple switched output in place of the regulator output. the gures in the charts on this page show the allowable power dissipation and estimated maximum current for vari- ous ambient temperatures and supply voltages. the data were taken using a standard fr4 board with minimal copper (r ja = 140oc/w), and using a "high k" dielectric board with copper ground plane and thermal vias (r ja = 80oc/w).
7 worcester, massachusetts 01615-0036 (508) 853-5000 115 northeast cutoff, box 15036 www.allegromicro.com data sheet 27463.1 a8420/a8421 lin bus transceiver with integrated voltage regulator preliminary ? subject to change without notice february 9, 2004 terminal list table name description number a8420 a8421 rx receive open drain logic output 1 1 en enable; logic input with internal pull-down 2 2 wake high-voltage input controlling modes: active (standby and normal) and inactive (sleep); with pull-up to vsup 33 tx transmit logic input with internal pull-up 4 4 gnd ground; connected to battery negative terminal 5 5 lin lin bus connection 6 6 vsup positive supply, 12 v nominal; external diode tted between the battery and this pin 77 inh (alternative to vreg) output providing a switched path to vsup 8 ? vreg (alternative to inh) output providing regulated 5 v at 30 ma ? 8 a8420l and a8421l 8-pin soic .196 .189 4.98 4.80 .157 .150 3.99 3.81 .244 .229 6.20 5.82 .022 ref 0.55 .050 bsc 1.27 .010 .004 0.25 0.10 .068 .053 1.73 1.35 .034 .016 0.86 0.41 .009 .007 0.23 0.18 8? 0? .004 bsc 0.10 .018 0.46 0.36 .014 dimensions in inches metric dimensions (mm) in brackets, for reference only 2 1 8 gauge plane seating plane
8 worcester, massachusetts 01615-0036 (508) 853-5000 115 northeast cutoff, box 15036 www.allegromicro.com data sheet 27463.1 a8420/a8421 lin bus transceiver with integrated voltage regulator preliminary ? subject to change without notice february 9, 2004 the products described here are manufactured under one or more u.s. patents or u.s. patents pending. allegro microsystems, inc. reserves the right to make, from time to time, such de par tures from the detail spec i ca tions as may be required to permit improvements in the per for mance, reliability, or manufacturability of its products. before placing an order, the user is cautioned to verify that the information being relied upon is current. allegro products are not authorized for use as critical compo- nents in life-support devices or sys tems without express written approval. the in for ma tion in clud ed herein is believed to be ac cu rate and reliable. how ev er, allegro microsystems, inc. assumes no re spon - si bil i ty for its use; nor for any in fringe ment of patents or other rights of third parties which may result from its use. copyright?2004 allegromicrosystems, inc.
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